This invention relates to a digital-analog converter, and more particularly, to a digital-analog converter suitable for use in converting a digital audio signal into an analog audio signal.
In compact disc players (CD players) or digital tape recording/playback devices (DAT devices), it is required that musical signals expressed in digital form be converted into analog signals prior to output.
As shown in FIG. 12, a commonly employed digital-analog converter (hereinafter referred to as a "DA converter") for playing back music includes a digital current converter 1 for converting digital data DT, which is inputted at a certain sampling period, into a direct current I.sub.o, a current-voltage converter 2 for converting the current I.sub.o into a voltage S.sub.D (see FIG. 13), and for holding the voltage, each time a sampling pulse P.sub.s is generated, and a low-pass filter 3 for forming the output voltage S.sub.D into a continuous, smooth analog signal S.sub.A, which is the output of the filter 3. The current-voltage converter 2 includes a switch S.sub.W having a movable contact changed over by the sampling pulse P.sub.s. When the movable contact is switched to a contact a, as shown in FIG. 12, an integrator is formed to generate the voltage S.sub.D, which conforms to the current I.sub.o. When the movable contact is switched to a contact b, a holding circuit is formed to hold the voltage S.sub.D.
The foremost problems encountered in the DA converter for music playback are the precision with which the digital data is converted into a current value, the speed at which the conversion is made and phase distortion caused by the low-pass filter.
The problems of conversion precision and conversion speed have largely been solved by higher speed LSI's and advances in trimming techniques. Though phase distortion ascribable to the low-pass filter can be mitigated by employing a digital filter, phase distortion cannot be eliminated completely so long as the filter is an integral part of the structure.
FIGS. 14(a) and 14(b) is useful in describing phase distortion. FIG. 14(a) illustrates an original audio signal waveform 5a, a 1 KHz component waveform 5b, and an 8 KHz component waveform 5c. FIG. 14(b) illustrates an audio signal waveform 6a outputted by the low-pass filter 3 (FIG. 12), a 1 KHz component waveform 6b, and an 8 KHz component waveform 6c. It will be understood from these waveforms that, due to the delay in the phase of the 8 KHz component, the output audio signal 6a is different from the original audio signal 5a, and that this phase distortion becomes particularly pronounced at high frequencies. Thus, the presence of the low-pass filter results in a major deterioration in sound quality.
As shown in FIG. 15, the low-pass filter output when a pulsed signal is applied to the filter is sluggish at a leading edge 7a and oscillates at an envelope portion 7b and trailing edge 7c. Consequently, when a musical signal exhibiting a large impulse variation is applied to the low-pass filter, sound quality changes greatly and there are times when even the rhythmical sense of the musical signal differs.
To overcome these disadvantages, the inventors have proposed a digital-analog converter which, as shown in FIG. 16, includes a unit pulse response signal generator 1 for generating unit pulse response signals SP (see FIG. 17), a digital data generator 2 for generating 16-bit digital audio data at a predetermined time interval .sub..DELTA. T, a multiplier 3 for multiplying a unit pulse response signal generated at a certain time by a predetermined item of the digital audio data, and a mixer 4 for producing an analog signal output by combining the unit pulse response signals that have been multiplied by the digital audio data. By way of example, refer to the specification of U.S. Ser. No. 171,812 (entitled "Digital-Analog Converter", filed on Mar. 22, 1988).
In accordance with this proposed digital-analog converter, the unit pulse response generator 1 partitions a unit pulse response signal SP at a predetermined time interval .sub..DELTA. T (see FIG. 17). When this is done, partial signals S.sub.-K .about.S.sub.K, which result from the partitioning operation, are repeatedly generated at the time interval .sub..DELTA. T, as shown in FIG. 18 (where only S.sub.-1, S.sub.0 and S.sub.1 are illustrated). The digital data generator 2 stores (2k+1) items of the latest 16-bit digital audio data V.sub.-K .about.V.sub.K, which are generated at the predetermined time interval .sub..DELTA. T, in internal shift registers while sequentially shifting the same. Multiplying-type DA converters in the multiplier 3 respectively multiply the partial signals S.sub.K by predetermined 16-bit digital audio data V.sub.-K stored in the shift registers corresponding to the partial signals. The mixer 4 combines the signals outputted by the multiplying-type DA converters, thereby producing an analog signal output S.sub.A (=.SIGMA.S.sub.K .multidot.V.sub.-K).
The inventors have proposed also a digital-analog converter in which the unit pulse response signal generator 1, rather than producing the partial signals S.sub.-K .about.S.sub.K, repeatedly outputs unit pulse response signals SP.sub.K (K=-4.about.4) per se at a period n.multidot..sub..DELTA. T, as shown in FIG. 19 (where n=9), the multiplication operation V.sub.-K .multidot.SP.sub.-K is executed by the multiplying-type DA converter 3 every time slot, and the multiplier outputs are mixed by the mixer 4 to obtain an output signal analog signal S.sub.A (=.SIGMA.V.sub.K .multidot.SP.sub.K). By way of example, refer to the specification of Japanese Patent Application No. 62-274803 (entitled "Digital-Analog Converter", filed on Oct. 30, 1987).
The partial signal waveforms S.sub.-K .about.S.sub.K inputted to the multiplying-type DA converter in the proposed first digital-analog converter become discontinuous at the interval .sub..DELTA. T, as shown in FIG. 18(a)-18(c). Therefore, a problem that arises is that, owing to a limitation on the settling time of this multiplying-type DA converter, the analog signal S.sub.A outputted by the mixer 4 picks up spike-shaped noise every .sub..DELTA. T. Moreover, the waveform of the analog signal S.sub.A when a unit pulse UP is inputted to the proposed digital-analog converter is as shown in FIG. 20(b). Though the analog signal S.sub.A must take on the waveform shown in FIG. 17 in a case where the unit pulse UP is applied, the waveform that results is one in which the analog signal picks up spike noise (glitch noise) every .sub..DELTA. T owing to the settling time of the multiplying-type DA converter.
With the second digital-analog converter, the unit pulse response signals SP.sub.K (K=-4.about.4) are repeatedly generated every 9.multidot..sub..DELTA. T, so that only some discontinuity occurs every 9.sub..DELTA. T. Consequently, glitch noise generated in each time slot is small in comparison with that produced in the first digital-analog converter.
The first digital-analog converter takes into consideration the fact that the unit pulse response signal SP (FIG. 17) is sharply attentuated prior to a time slot T.sub.-5 and after a time slot T.sub.5, and approximates the unit pulse response signal SP by nine partial signals S.sub.-4 through S.sub.4 in nine time slots S.sub.-4 through S.sub.4, respectively. For this reason, the proposed digital-analog converter requires nine partial signal generators, a memory circuit composed of nine shift registers, and nine multiplying-type DA converters. This is disadvantageous in terms of an increase in size and cost.
Accordingly, if it is attempted to approximate the unit pulse response signal by a fewer number of partial signals in an effort to reduce the number of partial signal generators, the number of shift registers in the memory circuit and the number of multiplying-type DA converters, the occurrence of glitch noise will be accompanied by a new problem, in which the frequency characteristic of the analog signal output undergoes a fluctuation in level in the audible band.
Similarly, with the second digital converter, nine unit pulse response signal generators, nine latch circuits and nine analog multipliers are required. This results in a large and costly arrangement.